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Remove some content from a verilog file

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http://www.unix.com – Hi, I have a verilog file which looks like Code: module xyz (x, y, z, a, b, c); input x; input y; input z; output a; output b; output c; initial begin ... end always ... ... endmodule What i want is to create a dummy of verilog module without the content so it should look like Code: module xyz (x, y, z, a, b, c); input x; input y; input z; output a; output b; output c; endmodule Any input is valuable. Thanks. Moderator's Comments: Please view this code tag video for how to (HowTos)